As the integrated circuit industry continues to explore techniques used to pack more circuits into a given semiconductor substrate, more and more thought is devoted to not only orienting the various devices in planar fashion along the surface of the substrate, but also to orienting the devices vertically. Typically, this is performed by either building up from the substrate surface or by burying devices in trenches formed within the face of the semiconductor body.
Parallel with an exponential growth in the use of integrated circuit ("IC") chips has been the development of numerous types of semiconductor memory devices. Advancements in semiconductor technology have made possible memory chips with millions of locations for storing bits of data information. While each generation of memory chips continues to quadruple the number of available storage locations, the size of the integrated circuit chip must yet be maintained within certain limits to enhance production yields and accommodate conventional packaging schemes.
One common memory cell employed in large integrated circuit memory chips comprises a static random access memory ("SRAM") cell wherein a bit is represented by the state of a circuit comprising a pair of cross-coupled inverters. A majority of SRAMs are fabricated using field effect transistor ("FET") technology. With appropriate voltage adjustment, these circuits can be reduced in area simply by scaling to a smaller dimension. Specifically, all dimensions of the various process masks can be uniformly shrunk so that the resulting circuitry is fabricated in a smaller area on the wafer. One obvious limitation of scaling an integrated circuit is the photolithographic technique used to form and maintain registration of the various masks. Thus, other methods for reducing the size of individual SRAM "cells" so as to increase the memory density on an IC chip are necessary.
Many different types of semiconductor trench constructions have been proposed in the art, all aimed at reducing the cell size of SRAMs and other circuit components without compromising the performance of the circuit. One approach taken in the art to conserve semiconductor wafer area is to form the transistors comprising the SRAM cell in a vertical orientation in a trench rather than in a lateral orientation across the surface of the substrate. However, as of this date, no complete SRAM cell has been formed in association with a single trench. Thus, a need exists for additional trench structures, particularly new multiple device trench structures which facilitate the fabrication of extremely high density IC chips